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TimeServoPTP Features TimeServo’s Capabilities Plus:
- An IEEE 1588v2 PTP Compliant Ordinary Clock (OC) Slave Implementation for FPGA
- Supports both 1-Step and 2-Step synchronization with an external network time grandmaster
- TimeServoPTP Delay Requests are 1-Step using MAC TX Hardware Time Insertion
- End to End (E2E) Delay Mechanism
- Single-component solution for providing coherent time within an FPGA
- Communicates with PTP Master via Ethernet L2 PTP/1588 EtherType frames
- Flexible and independent clocks for control-plane and reference clock
- Up to 32 time “now” outputs with Clock Domain Crossing (CDC) Logic
- Each in their own Clock Domain from user-supplied clock
- Each individually selectable 80b output format (Binary, IEEE Ordinary, IEEE Transparent)
- Each with a Pulse Per Second (PPS) output pulse in output clock domain
- Software control and observability from AXI control plane
- Following Initialization, no interaction from host is required
- Atomic Rules implementation of a Gardner Type-2 Digital Phase Locked Loop (DPLL)
- FPGA Resources Used (Includes TimeServo and Other Sub-Cores)
- ALMs/LUTs: 13K
- M20Ks/BRAMs: 17
- DSPs: 6
- Supported FPGA devices include Intel Agilex and Xilinx UltraScalePlus