Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo is used where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity.

In conjunction with a timestamp-capable MAC (not included), TimeServo can be ordered as TimeServoPTP: a complete IEEE-1588v2/PTP ordinary slave device. TimeServoPTP does not require any host processor interaction to function.
Key Features
- Single-component solution for providing coherent time within an FPGA
- Operates with or without an externally provided Pulse-Per-Second (PPS) Reference
- Flexible and independent clocks for control-plane and reference clock
- Up to 32 outputs, each in their own clock domain
- Outputs individually runtime switchable between three 80-bit formats
- Binary 48.32
- IEEE Ordinary
- IEEE Transparent
- Software control and observability from AXI control plane
- Internal logical 120-bit resolution phase accumulator
- Proportional/Integral controlled Digital Phase Locked Loop (PI-DPLL)
- Observable output of digital Phase-Frequency Detector (PFD Monitor)
Specifications
- Standard AXI4-Lite Control Plane Interface
- Up to 32 80-bit time outputs, runtime switchable binary and IEEE ordinary/transparent
- Internal logical 120-bit Reference Clock Phase Accumulator
- Proportional/Integral controlled Digital Phase Locked Loop (PI-DPLL)
- Nominal Settling time: 150 s (may be changed under software control)
- Best-Case Simulated Jitter Observation +/- 2.5 ns (with 400 MHz Reference Clock)
- Nominal Real-World Jitter Observation +/- 10 ns (with 400 MHz Reference Clock)
Provided Examples
- Software control utility to set/get common settings as well as observe behavior.
- Standalone jtag/usb observation of IEEE-1588v2/PTP Ordinary Slave capability without any need for host PCIe link. (With TimeServoPTP only.)