Arkville FPGA Gen5 PCIe DMA IP

Seamlessly transport data between FPGA logic and host memory at up to 60 GBytes/s (480 Gbps) in each direction.

Arkville provides a high-throughput, low-latency conduit between host memory and FPGA fabric logic, offloading CPU core usage, eliminating memory copies, and improving overall efficiency.

Arkville FPGA : Host Memory Data Mover IP Solution chip2

Software engineers see industry-standard APIs for producing and consuming data in zero-copy user space memory buffers on the host.

Hardware engineers see industry-standard RTL interfaces to produce and consume the same data.

Arkville_TopLevelDiagram_170206

Key Features and Benefits

  • Trusted and Performant FPGA PCIe DMA
  • Offload server cycles to FPGA gates
  • Bring your FPGA-based packet processing solutions to market quickly
  • Future proof your GPP/FPGA application with DPDK and AXI standards
  • FPGA Vendor Agnostic RTL
  • Support for both Intel/PSG and AMD/Xilinx FPGA devices
  • Open-Source “net/ark” Arkville driver in DPDK 23.11

Other Features

  • Concurrent, Full-Duplex Upstream and Downstream Data Movement
  • AXI Streaming interfaces for packet movement
  • Up to 1 Tbps burst traffic (Two 128 Byte wide, 500 MHz, AXI streams)
  • Dedicated Application BAR (ABAR) AXI4-Master for the FPGA Application
  • Tested extensively in with Jenkins CI/CD

Provided Examples

  • Atomic Rules provides Arkville example designs that may be used as a starting point for your own solutions. These include:
    • Four-Port, Four-Queue 10 GbE example (Arkville + 4×10 GbE MAC)
    • Single-Port, Single-Queue 100 GbE example (Arkville + 1×100 GbE MAC)

Request the Arkville FPGA / Host Memory Data Mover IP Solution datasheet