Seamlessly transport data between FPGA logic and host memory at up to 220 Gb/s.
Arkville provides a high-throughput, low-latency conduit between host memory and FPGA fabric logic, offloading CPU core usage, eliminating memory copies, and improving overall efficiency.
Software engineers see industry-standard APIs for producing and consuming data in zero-copy user space memory buffers on the host.
Hardware engineers see industry-standard RTL interfaces to produce and consume the same data.
Key Features and Benefits
- Offload server cycles to FPGA gates
- Bring your FPGA-based packet processing solutions to market quickly
- Future proof your GPP/FPGA application with DPDK and AXI standards
- Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
- Up to 230 Gbps sustained with a PCIe Gen4x16 interface
- FPGA Vendor Agnostic RTL
- Allows for immediate operation with Intel’s Agilex-F, Xilinx Virtex® UltraScale™ and UltraScale+™ FPGA devices
- Open-Source “net/ark” Arkville driver in DPDK 22.03
o Ready-to-Go Solution to FPGA/GPP Packet Movement
o 4 Physical Queue-Pairs (RX/TX) Standard; Up to 64 Physical Queue-Pairs
o Single PCIe Physical Function (PF) supporting multiple ports
o Concurrent, Full-Duplex Upstream and Downstream Data Movement
- GPP / SOFTWARE SPECIFIC DPDK Arkville PMD in DPDK 22.03
o Tested extensively in with DPDK Test Suite (DTS)
o Unencumbered Application BAR (ABAR) for FPGA Application
- FPGA / HARDWARE SPECIFICo AXI Streaming interfaces for packet movement
o Up to 512 Gbps, 1G pps burst traffic (Two 64 Byte wide, 450 MHz, AXI streams)
o Dedicated Application BAR (ABAR) AXI4-Master for the FPGA Application
- Atomic Rules provides Arkville example designs that may be used as a starting point for your own solutions. These include:
o Four-Port, Four-Queue 10 GbE example (Arkville + 4×10 GbE MAC)
o Single-Port, Single-Queue 100 GbE example (Arkville + 1×100 GbE MAC)