News
Atomic Rules introduces the world’s highest performance PCIe host interface for Intel Agilex F-Series FPGAs
Auburn, NH – December 14, 2021 – Atomic Rules LLC, a supplier of enterprise-grade FPGA IP cores and solutions, today announced the extension of its established Arkville data mover to support Intel Agilex F-Series FPGA devices. Atomic Rules Arkville data mover provides a high-throughput, low-latency conduit between host memory and FPGA fabric logic, offloading CPU…
Read MoreAtomic Rules launches TimeServo System Timer IP Core for FPGA
Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component AUBURN, NH – Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of TimeServo, a Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component. Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically…
Read MoreAtomic Rules announces DPDK-aware FPGA/GPP data mover
Systems requiring Linux kernel bypass can now offload server cycles to FPGA gates AUBURN, NH – Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of Arkville, a DPDK-aware FPGA/GPP data mover enabling Linux DPDK applications to offload server cycles to FPGA gates. “Our Arkville launch brings five man-years of DPDK-first…
Read MoreAtomic Rules is proud to become a member of The Linux Foundation
Atomic Rules is proud to become a member of The Linux Foundation alongside ARM, AT&T, Cavium, Intel, NXP, Red Hat, ZTE Corporation, 6WIND, Huawei, Spirent, Wind River, KAIST, University of Limerick, University of Massachusetts Lowell, and Tsinghua University. Click to access the official Linux Foundation press release.
Read MoreAtomic Rules COTS Journal Article: Internet Transport Protocols Contend for Military Interconnect Role
Think UDP is lossy? Atomic Rules shows how transceivers tech evolution disrupts this legacy assumption. UDP now a serious contender in multicomputer interconnect when costs and time-to-deployment are key concerns (click below to see military radar use case on page 17). https://issuu.com/features?issuu_product=creatorhub_redirect
Read More100GbE and PCIe Gen3 x16 demo – leveraging DPDK for FPGA+CPU computational packet processing
Xilinx, BittWare, and Atomic Rules leveraging Intel Corporation’s DPDK to achieve 150Gbps line rate on mixed FPGA/CPU architecture. Click to access Xilinx Xcell Daily blog for more details.
Read MoreBittWare and Atomic Rules announce an FPGA-based UDP Offload Engine IP Core for 10/25/50/100 GbE
Hardware-based acceleration dramatically improves throughput and provides a simple path to 50 and 100 GbE. CONCORD, NH & WASHINGTON D.C. – BittWare, a premier FPGA board supplier for over 25 years, has collaborated with Atomic Rules, a reconfigurable computing IP firm, to announce a UDP Offload Engine (UOE) IP core today at the FCCM 2016 Symposium.…
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