Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component 

AUBURN, NH – Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of TimeServo, a Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component.

Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use
where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity.

Learn more: TimeServo – System Timer IP Core for FPGA

In conjunction with timestamp-capable MACs (not included) and host-control software (as-is examples provided),
TimeServo is a vital and central component of an IEEE-1588/PTP system.AtomicRules TimeServo

AtomicRules TimeServo

TimeServo IP Core Pricing and Availability

The Atomic Rules TimeServo IP core for FPGA is available for purchase. TimeServo includes “As is” software control utility to set/get common settings as well as observe behavior and example design using Atomic Rules Arkville (Arkville NOT Included) showing application with IEEE-1588 Precision Time Protocol (PTP). Contact us for pricing information.

About Atomic Rules

Atomic Rules is an electrical engineering consultancy providing its clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Their practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors. Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, they use tools and techniques inspired by functional programming. Beyond RTLs, they specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques – not reinvent them. For more information, visit

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